Process for forming portions of a compound material inside a cavity and an electronic circuit manufactured therefrom

ABSTRACT

A process for forming portions of a compound material within an electronic circuit includes the formation of a cavity having at least one opening facing onto an access surface. The cavity furthermore has an internal wall with at least one region made of an initial material (for example, silicon). A metal is deposited close to the region of initial material. The circuit is then heated to form a portion of the compound material (for example, a silicide) in the region of initial material inside the cavity. The compound material is formed from elements of the initial material and from some of the metal deposited. The excess metal that has not formed some of the compound material is then removed from the cavity.

PRIORITY CLAIM

[0001] The present application claims priority from French Applicationfor Patent No. 02 11989 filed Sep. 27, 2002, the disclosure of which ishereby incorporated by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Technical Field of the Invention

[0003] The present invention relates to a process for forming portionsof a compound material inside a cavity of an integrated circuit deviceand to an electronic circuit incorporating portions of compound materialthus obtained.

[0004] 2. Description of Related Art

[0005] The increase in electrical performance and level of integrationof electronic circuits requires the design and fabrication of circuitshaving complex geometrical configurations. As an example, somefield-effect transistors or MOS (Metal Oxide Semiconductor) transistorshave a gate which completely surrounds the channel of these transistorsso as to obtain better control of the conduction state of thetransistor. A conducting part of the gate must therefore be formedbeneath the channel, that is to say between the channel and a subjacentsubstrate that supports the circuit. Such MOS transistors are known asGAA (Gate All Around) transistors.

[0006] It is possible to fabricate such GAA transistors by superposingportions of materials formed in succession from the surface of asubstrate, as a stack of these portions. In this case, the lower part ofthe gate is firstly formed above the substrate using a conductingmaterial, then the channel, generally based on silicon, is formed abovethis lower gate part, and the gate is completed by forming the uppergate part above the channel. Lateral parts of the gate may be formed atthe same time as the lower part or as the upper part, but at least twosteps for forming the various parts of the gate are needed, making thetransistor fabrication process relatively long.

[0007] In general, producing a single conducting element in severalseparate steps gives rise to inhomogeneities within this element, evenif the element consists of a single material used in each step of itsproduction. Such inhomogeneities have an undesirable effect on the finalelectrical behavior of the element.

[0008] Moreover, it is known to produce portions of ametal-silicide-type material selectively in defined regions of anelectronic circuit. To do this, silicon is initially placed in theseregions and, at a stage in the circuit fabrication process in whichthese regions are exposed, the circuit is covered with a layer of ametal capable of forming a silicide-type compound. The circuit is thenheated so as to form this silicide compound in the regions where themetal is in contact with the silicon. After the heating, the metal partsdeposited outside the silicon regions therefore remain unaffected andare removed, for example by dissolving them in a suitable chemicalsolution. Since the silicide is insoluble in the solution used, itremains in the final circuit within the initial silicon regions.

[0009] This method of forming silicide portions has a drawback in thatthe silicon regions within which the silicide is formed must beinitially exposed. This constraint may be incompatible with a complexconfiguration of the electronic circuit.

[0010] There is accordingly a need to overcome this drawback in theproduction of integrated circuit devices.

SUMMARY OF THE INVENTION

[0011] The present invention is generally directed to allowing theformation of portions of a compound material in circuit regions that areinitially buried, that is to say covered by other constituent materialsof the circuit.

[0012] The present invention provides a process for forming at least oneportion of a compound material formed from elements of an initialmaterial and of a metal within an electronic circuit, comprising thefollowing steps:

[0013] (a) formation of a cavity that includes at least one opening ontoan access surface and has an internal wall having at least one region ofinitial material;

[0014] (b) deposition of a metal close to said region of initialmaterial;

[0015] (c) heating of the circuit so as to form a portion of thecompound material in said region of initial material; and

[0016] (d) removal of at least one portion of the metal that has notformed some of the compound material from the cavity via said opening.

[0017] According to the invention, a cavity is firstly formed in thecircuit, inside which portions of a compound material are selectivelyformed from regions of initial material within the cavity. The compoundmaterial is formed after deposition in the cavity of a metal which iscapable of reacting with the initial material to form the compoundmaterial from elements of the initial material and the metal. The excessmetal that has not formed some of the compound material is then removedfrom the cavity.

[0018] One advantage of the process of the invention is that it iscompatible with many configurations of the electronic circuit. This isbecause various methods for forming the cavity can be used, and selectedaccording to each circuit configuration.

[0019] The cavity formed may especially include a cylindrical orparallelepipedal first volume open to the access surface so as to form,for example, a well starting from an exposed surface of the circuit.

[0020] It may also include a second volume into which the first volumeruns on the opposite side from the access surface, the second volumeextending further than the first volume parallel to the access surface.In this case, the cavity forms a cave connected via a narrow well to theexposed surface of the circuit. The cavity may furthermore have one ofthe above shapes, opening onto a sidewall of the circuit and beingparallel, perpendicular or at any orientation to a surface of asubstrate carrying the circuit.

[0021] Another advantage of the process of the invention is that thereare many possible ways of arranging the portions of compound material,resulting from the initial arrangement of the regions of initialmaterial within the circuit and from the shape of the cavity in theseregions. Thus, portions of compound material having the general shape ofa pad may in particular be oriented parallel or perpendicular to theaccess surface.

[0022] In a geometrical configuration in which the electronic circuit isplaced on a substrate and in which the cavity includes a chimneyapproximately perpendicular to the surface of the substrate, the chimneyallows access to a buried part of the circuit in order to form theportions of compound material. The process of the invention is thereforeparticularly suitable for circuit structures having several superposedlevels of components, or of parts of components, and contributes to areduction in the cost of the electronic circuit, this reduction beingdue to a reduction in the size of the substrate.

[0023] Yet another advantage of the process of the invention is thepossibility of forming several portions of compound material within thecircuit simultaneously. To do this, several regions of initial materialmust be provided in the circuit, and the cavity is formed so as to reachthese regions. Optionally, the circuit may also include regions ofinitial material outside the cavity, where the compound material isformed simultaneously with the portions of compound material formedinside the cavity.

[0024] The cavity may be formed in various ways depending on theconfiguration of the circuit. In particular, it may be formed byremoving at least one material of the circuit, especially from theaccess surface.

[0025] Another method for forming the cavity comprises transferring atleast one material between a temporary substrate and a final substratecarrying the electronic circuit.

[0026] Optionally, these two methods may be combined to obtain a cavitywhose shape is tailored to the configuration of the circuit and to thedesired arrangement of the portions of compound material. The formationof the cavity may also include a step of constructing materials in agiven pattern on the circuit, the pattern helping to define the cavity.

[0027] The initial material may comprise silicon, germanium, arsenic,selenium, or a mixed compound comprising at least one of the aboveelements. When the initial material comprises silicon, the compoundmaterial formed is of the metal silicide type.

[0028] Step (b) of the process may be carried out in two different ways,depending on the size of the cavity and of its opening onto the accesssurface. When the cavity and its opening are large enough, step (b) maycomprise introducing the metal into the cavity via said opening so as todeposit the metal on at least said region of initial material.

[0029] If the cavity and its opening are too small in size to introducethe metal via the opening during deposition of the metal, step (b) thencomprises depositing the metal outside the cavity, close to saidopening. During the heating of step (c), the deposited metal diffusesinto the cavity, via said opening in the cavity, as far as said regionof initial material, so as to form a portion of the compound material insaid region of initial material.

[0030] Several different methods can be used to introduce the metal intothe cavity. For example, CVD (Chemical Vapor Deposition) may be used todeposit the metal chemically, starting from gaseous precursor compoundsincorporating metal atoms. Such a deposition method is preferablycarried out at reduced pressure, in order to allow the metal to bedeposited on sides of the cavity that are remote from its opening ontothe access surface. Under special conditions, the metal may be depositedby such processes in successive and continuous atomic layers.

[0031] Other possible methods for depositing the metal in the cavity usea chemical solution introduced into the cavity, which incorporatesdissolved compounds based on the metal in an oxidized form. In one ofthese methods, called the electroless method, reducing compounds arethen added to the solution, which cause the metal to be released in theform of a conducting layer coating the cavity.

[0032] The metal deposited using one of the above methods, and capableof forming a compound material, may be cobalt, tantalum, tungsten,titanium, aluminum, copper, silver, platinum, nickel, or an alloycomprising at least one of these metals. The compound material formedmay be electrically conducting, depending on the role of the portions ofcompound material within the electronic circuit.

[0033] The operation of introducing the metal into the cavity, in orderto deposit it in the region or regions of initial material inside thecavity, is preferably carried out so as not to completely fill thecavity. Thus, any stresses that appear during heating and duringformation, in the cavity, of the compound material are limited. Thiselectronic circuit caused by such stresses.

[0034] The process of the invention may furthermore be used to connect,via bridges of compound material, several regions of initial materialwithin the cavity. To do this, the internal wall of the cavity has atleast two regions of initial material separated by an intermediateregion of a material other than the initial material. During step (c) inwhich the circuit is being heated, the initial material of at least oneof said regions of initial material is made to diffuse into the metal soas to form a portion of compound material connecting said regions ofinitial material.

[0035] The invention also relates to an electronic circuit comprising aportion of compound material formed in the manner described above. Inparticular, the portion of compound material may constitute at least oneelectrical connection within this circuit.

[0036] The invention also relates to an MOS transistor comprising a gatehaving a portion of compound material formed using the above process,and to an electronic circuit comprising such an MOS transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0037] A more complete understanding of the method and apparatus of thepresent invention may be acquired by reference to the following DetailedDescription when taken in conjunction with the accompanying Drawingswherein:

[0038]FIGS. 1a and 1 b are perspective views of a field-effecttransistor during fabrication according to a first method ofimplementing the invention;

[0039]FIGS. 2a-2 d are sectional views, on the plane II-II indicated inFIGS. 1b and 3 a-3 d, illustrating successive steps in the fabricationof the transistor of FIG. 1 in accordance with the first method ofimplementing the invention;

[0040]FIGS. 3a-3 d are sectional views, on the plane III-III indicatedin FIGS. 1b and 2 a-2 d, illustrating the same successive steps in thefabrication of the transistor;

[0041]FIGS. 4a-4 d are sectional views, on the plane IV-IV indicated inFIGS. 1b and 2 a-2 d, illustrating the same successive steps in thefabrication of the transistor;

[0042]FIG. 5 is a perspective view of this transistor in the state shownin FIGS. 2d, 3 d and 4 d; and

[0043] FIGS. 6 to 13 are sectional views showing various steps in theproduction of electrical connections using another method ofimplementing the invention.

DETAILED DESCRIPTION OF THE DRAWINGS

[0044] In the FIGURES, for the sake of clarity, the dimensions of thevarious parts of the components or circuits shown are not in proportionto their actual dimensions.

[0045]FIGS. 2a-2 d, 3 a-3 d, 4 a-4 d and 6-13 are sectional views of atleast one substrate and of various materials placed on a planar surfaceof this substrate. The sectional views are taken in planes perpendicularto the surface of the substrate. In the FIGURES, identical referencescorrespond to similar elements. N denotes the direction perpendicular tothe surface of the substrate and oriented upwards in the FIGURES, thesubstrate being placed in the lower part of the FIGURES. The terms “ontop of”, “beneath”, “on”, “under”, “upper” and “lower” used hereafterrefer to this orientation.

[0046] A first method of implementing the process of the invention willnow be described in detail within the context of the fabrication of aGAA-type MOS transistor, the gate of which is made of a metal silicide.

[0047]FIG. 1a is a perspective view of a transistor 1 in the course offabrication. The transistor 1 is fabricated on top of a substrate 100,for example made of silicon, covered with a layer 101 of insulatingmaterial, for example silica SiO₂. A silica rim 102, of rectangularsection, placed on the layer 101 surrounds a rectangular portion of thatupper surface of the layer 101 which is occupied by the transistor 1 anddefines a central depression.

[0048] This depression is filled with a temporary material 103, such asa silicon-germanium alloy, up to about two thirds of the height of therim 102.

[0049] A first transverse structure, the ends of which are referenced Sand D, connects two opposed sides of the rim 102, bearing on the latterat each of its ends and on the temporary material 103 in its centralpart.

[0050]FIG. 2a shows a section of the transistor 1 being fabricated in avertical plane of symmetry II parallel to the first transversestructure. The central part of this structure is formed by a bar 3 ofsilicon, possibly single-crystal silicon, surrounded by a silica layer4. The layer 4 extends between the two opposed sides of the rim 102beneath the bar 3, as can be seen in FIG. 2a, and is present on top ofthe bar 3 only in a central part of the latter. In this central part,the layer 4 is furthermore covered with a portion of a silicon volume 2flanked by two vertical walls 5 of electrically insulating material, forexample silicon nitride Si₃N₄. The first transverse structurefurthermore includes, at each of its ends bearing on the rim 102, twoinsulating edges 5, also made of silicon nitride. These insulating edgesare each connected to the vertical walls 5 which flank the portion ofsilicon volume 2 via two other silicon nitride walls that run along thesidewalls of the first structure.

[0051] A second transverse structure intersects the first transversestructure at right angles, bearing on the other two opposed sides of therim 102 and on the temporary material 103. The temporary material 103may have a central raised part beneath the second transverse structure,which follows the shape of the lower surface of this second transversestructure seen in FIG. 3a. FIG. 3a corresponds to a section of thetransistor 1 being fabricated in a vertical plane of symmetry IIIparallel to the second transverse structure. The silicon volume 2 formsthe main part of the second transverse structure and completelysurrounds, at its center, the first transverse structure. Additionalwalls of silicon nitride cover the side walls of the second transversestructure, these being connected to the silicon nitride walls of thefirst transverse structure at each internal corner of the intersectionof the two transverse structures.

[0052]FIG. 4a is a third section of the transistor 1 in a vertical planeIV parallel to the plane III, but offset with respect to the latter asindicated in FIG. 2a, so as to intersect the first transverse structureoutside the upper part of the silicon volume 2. FIG. 4a shows a sectionof the first transverse structure, composed of the silicon bar 3surrounded laterally and underneath by the silica layer 4. This layer 4separates the bar 3 from the lower part of the silicon volume 2. Theassembly is flanked by two insulating side walls 5. FIG. 1a shows therelative arrangements between the insulating walls 5 shown in FIGS. 2aand 4 a, respectively.

[0053] The above structure is produced using techniques, known to thoseskilled in the art, that combine masking and material deposition andetching steps repeated so as to form all the superposed or juxtaposedvolumes according to FIGS. 1a, 2 a, 3 a and 4 a.

[0054] The silicon bar 3 of the first transverse structure is intendedto form the main conducting path of the transisitor 1 in its finalconfiguration. Thus, the left end of the first transverse structure inFIGS. 1a and 2 a corresponds to the source S, the right end correspondsto the drain D and the central part of the bar 3, visible in FIG. 2a,corresponds to the channel CA of the transistor 1.

[0055] In particular, when producing the structure 1 corresponding toFIGS. 2a, 3 a and 4 a, the silicon bar 3 is appropriately doped, in amanner known to those skilled in the art, in order to exhibit conductioncharacteristics suitable for use of the transistor 1 as a transistor forswitching between an on state and an off state, as a control transistor,as a power transistor or as a transistor more especially suitable forany other use.

[0056] Those parts of the volume 2 lying above and below the channel CAare intended to form, in the rest of the process according to theinvention, the upper part GS and the lower part GI of the gate thatsurrounds the channel CA in the plane of FIG. 3a.

[0057] During a first step of the process according to the invention thetemporary material 103 is removed from its surface portions exposedbetween the ends of the arms of the first and second transversestructures, inside the rim 102. When the temporary material 103 is asilicon-germanium alloy, one method of selective removal that can beused comprises bringing the exposed parts of the material 103 intocontact with an aqueous chemical etching solution which is bothoxidizing and acid, composed for example of 40 milliliters of 70% nitricacid HNO₃, 20 milliliters of hydrogen peroxide H₂O₂ and 5 milliliters of5% hydrofluoric acid HF. The silicon-germanium alloy is selectivelydissolved in this solution, whereas the other materials of thetransistor 1, namely the pure or doped silicon, the silica and thesilica nitride in the example in question, are left intact.

[0058] The configuration of the transistor 1 obtained after thisselective removal is shown in FIG. 1b. This figure shows the twotransverse structures in the form of two respective bridges bearing viatheir ends on the rim 102, the second structure surrounding the first atthe intersection between the two structures. The space initiallyoccupied by the temporary material 103 now corresponds to a cavity Cthat extends under the two between the arms of the transverse structuresand the corners of the rim 102. FIGS. 2a, 3 a and 4 a correspond to thefabrication stage shown in FIG. 1b, that is to say after the temporarymaterial 103 has been selectively removed.

[0059] During a second step, a metal capable of forming a silicidematerial is deposited on the exposed surfaces of the transistor 1 andinside the cavity C.

[0060] This metal may be deposited using one of the processes known tothose skilled in the art such as, for example, chemical vapor deposition(CVD). To do this, gaseous precursors, possibly of the organometallictype, are brought into contact with the transistor 1 and react on theexposed surfaces, forming a layer of said metal. Owing in particular tothe low gas pressure maintained around the transistor 1 duringintroduction of the precursors, the latter penetrate into the cavity Cvia the openings O and cover its entire wall, including in that partfacing the inside of the cavity C.

[0061]FIGS. 2b, 3 b and 4 b are sections corresponding to FIGS. 2a, 3 aand 4 a, respectively, and show the transistor 1 after the metal hasbeen deposited. The deposited metal forms a continuous layer 6 coveringthe upper, lateral and lower faces of the two transverse structures, thebottom of the depression formed by the silica layer 101, the variousparts of the silicon nitride spacer 5 and the silica rim 102 on itsvertical and horizontal faces.

[0062] The metal employed for the layer 6 may in particular be cobalt.

[0063] The transistor 1 is then heated to a temperature suitable forforming a compound of the metal silicide type. This compound is formedin the silicon and/or polysilicon regions present at the surface of thetransistor 1 or inside the cavity C, in contact with the layer 6. Thesesilicon-metal 6 contact regions are the upper surfaces of the ends S andD of the bar 3, and the upper, lower and lateral surfaces of the volume2.

[0064] The heating temperature, which depends on the metal of the layer6, is for example between 500° C. and 700° C. During heating, metal fromthe layer 6 diffuses into the silicon of the aforementioned regions,starting from their surfaces, and silicon diffuses into the layer 6,forming a volume of mixed silicon-metal composition around the initialcontact surface between the silicon and the metal. This mixedcomposition essentially corresponds to a compound of metal silicidetype, which is electrically conducting. In the particular case ofcobalt, the volume finally occupied by the silicide compound is about3.5 times the volume occupied by the initial silicon converted intocobalt silicide.

[0065]FIGS. 2c, 3 c and 4 c show the metal silicide portions 26, 36S and36D formed, namely on top of the bar 3 and over the entire exposedsurface of the initial volume 2, that is to say the upper surface of thevolume 2, the sides and the lower surface (inside the cavity) of thevolume 2. The rounded shapes shown correspond to the increase in volumeof the materials involved in the silicide formation reaction.

[0066] Optionally, residual silicon portions of the volume 2 may remainwithin the silicide formed, these being shown in FIG. 3c, but preferablythe amount of metal of the layer 6 is sufficient to allow all, or almostall, of the silicon of the volume 2 to be converted into silicide.

[0067] By contrast, the thickness of the bar 3 in the direction N issufficient for only a limited fraction of the silicon of the bar 3 to beconverted into silicide, thus forming an upper silicide coating on theends S and D of the bar 3.

[0068] Those parts of the metal layer 6 that have not formed a silicideare then removed using a selective removal process known to thoseskilled in the art. This removal is preferably carried out by isotropicchemical etching using a liquid solution incorporating chemicalreactants selected for specifically dissolving the metal 6. Acidreactants, possibly having a combined oxidizing effect, such as nitricacid HNO₃, are particularly suitable. During this removal, the liquidsolution dissolves the metal and advances into the cavity C via thespace left free by the dissolved metal, until the entire residual spaceof the cavity C has been filled and the residues of the metal layer 6 init have been completely dissolved.

[0069]FIGS. 2d, 3 d, 4 d and 5 show the transistor 1 after this removal.The silicide portions 36S and 36D form the electrical contacts in thesource region S and drain region D of the transistor 1, respectively.The silicide volume 26 also constitutes the gate surrounding the channelCA, with the upper part GS and lower part GI of this gate.

[0070] This gate is extended by silicide lands as far as the opposedsides of the rim 102 (FIGS. 3d and 5), these replacing the two ends ofthe second initial transverse structure. These lands may serve inparticular as electrical connections, connecting the gate to componentsexternal to the transistor 1. In addition, the gate has two otherextensions under the ends of the source S and the drain D of the bar 3,one of them being visible in FIG. 4d, contributing to particularlyprecise control of the electrical state of the transistor 1 obtained.

[0071] Cobalt was mentioned as an example of the metal 6. Any othermetal capable of forming an electrically conducting silicide compoundmay also be used.

[0072] Preferably, the metal 6 is chosen in such a way that thecorresponding silicide has a work function lying within a range of ±25%around the mean value of the two work functions of a p-doped siliconmaterial and an n-doped silicon material respectively. For such a metal,n-type or p-type complementary MOS transistors, produced using theprocess described, have trigger voltages equal in absolute value but ofopposite signs. Such opposite values of the trigger voltages simplifythe design of electronic circuits comprising the two types oftransistor.

[0073] Moreover, the siliciding process according to this first methodof implementing the invention allows the gates of the two types oftransistor to be produced simultaneously, these being distinguishedbeforehand by the type of the doping of their respective bars 3.

[0074] The process of the invention will now be illustrated by thedescription of a second method of implementation, particularly suitablefor producing electrical connections between separate circuit portions.

[0075]FIG. 6 shows a plane substrate 100, for example made of silicon,covered with a layer for electrical insulation 101, for example made ofsilica SiO₂. The insulation layer 101 is itself covered by severalportions of different materials, arranged as shown in the left-hand partof FIG. 6.

[0076] A portion of a temporary material 110 may comprise, for example,a silicon-germanium alloy similar to that used in the first method ofimplementing the process of the invention described above. On one sideof the portion of temporary material 110, a first silicon portion 10 aformed on the insulation layer 101 is contiguous with the portion 110,over about one half of the height of the portion 110. On the oppositeside of the portion 110, a second silicon portion 15 is also contiguouswith the portion 110, over the entire height of the latter. A volume 11of silica SiO₂ completes the structure supported by the substrate 100 upto a uniform height, in the direction N, equal to the height of theportion 110 of temporary material.

[0077] A second planar substrate 200, possibly also made of silicon,supports a volume 12 of silica SiO₂ on its upper surface, with anintermediate silica layer 201. Several silicon portions 10 b, 13 a, 13 band 14 have been provided in the volume 12, using processes known tothose skilled in the art, combining silicon deposition andetching/masking steps. These portions 10 b, 13 a, 13 b and 14 aredistributed within the volume 12, as shown in the right-hand part ofFIG. 6.

[0078] The upper surfaces S1 and S2 of the structures supported by thesubstrates 100 and 200, respectively, are then polished so as to makethem strictly planar and free of surface contamination.

[0079] The substrate 200 is then inverted and placed on top of thesubstrate 100 with the surface S2 applied against the surface S1. A bondis then formed between the materials of the surfaces S1 and S2, bondingthe substrates 100 and 200 together, using the process called waferbonding.

[0080]FIG. 7 shows the structure thus obtained. The substrate 200 isthen removed by polishing, from its surface on the opposite side fromthe substrate 100 towards the S1/S2 bonding interface. Optionally, thesilica layer 201 is also partially removed during this polishing. Itsablation is completed by selective plasma etching (or dry etching), forexample by introducing a gas capable of etching silica, such as C₄F₈,into the plasma.

[0081] Next, a resist mask M is produced by lithography on top of thevolume 12. The mask M has an opening O via which the upper surface ofthe volume 12 is exposed to a directional flux F of an etching plasma(FIG. 8).

[0082] The composition of this plasma may, in particular, be identicalto that used to ablate the silica layer 201. A first volume V1 is thusetched away within the volume 12, forming a chimney for access to theportion 110 of temporary material (FIG. 9).

[0083] The opening O in the etching mask M has been positioned on thevolume 12 in such a way that the chimney V1 reaches the silicon portion10 b at that end of this portion lying above the portion 110 oftemporary material. The etching mask M is then removed.

[0084] A solution for selectively dissolving the silicon-germanium alloyof the portion 110 is then introduced via the chimney V1. This solutionmay be identical to that used in the first method of implementing theinvention described above. The alloy of the portion 110 is thendissolved so as to form a second empty volume V2 (FIG. 10).

[0085] Next, a layer of metal 6, for example cobalt, is deposited overthe entire structure obtained, so as to cover the upper surface of thevolume 12 and the wall of the volumes V1 and V2, which join together toform a cavity C (FIG. 11).

[0086] Preferably, the metal is deposited at low pressure so as toobtain sufficient penetration, by diffusion, of the metal precursorsused in this deposition into the cavity C. Thus, the entire wall of thecavity C is covered with metal, in sufficient quantity. Advantageously,the cavity C is not completely filled.

[0087] The substrate 100 is then heated to form a silicide at thesurfaces of contact between the silicon and the layer of metal 6. Thesilicide is then formed on the parts of the wall of the cavity that areadjacent to the silicon volumes 10 a, 10 b and 15 (FIG. 12). Thanks tothe part of the volume of the cavity C that has been left empty duringdeposition of the metal 6, no excessive stress is generated duringformation of the silicide in the cavity C liable to disturb thearrangement of the various materials on the substrate 100.

[0088] The metal 6 was deposited inside the cavity C in sufficientquantity so that, during heating to form the silicide, the silicon ofthe portion 15 is entirely converted into silicide so as to constitutethe silicide portion 156 visible in FIGS. 12 and 13.

[0089] Moreover, the two silicon portions 10 a, 10 b, the ends of whichface onto the cavity C, are initially isolated by a part of the silicavolume 11. During the heating step, silicon atoms coming from theseportions 10 a, 10 b diffuse into the deposited metal 6 and thus form aconducting bridge of silicide material 106 electrically connecting thetwo portions 10 a, 10 b.

[0090] This silicide bridge can then form an electrical connectionbetween two electronic components, such as transistors, comprising oneof the two silicon portions 10 a, 10 b respectively.

[0091] Likewise, outside the cavity C, the silicon portion 14 on theupper surface of the volume 12 is converted into a silicide portion 146,consuming all the silicon initially present in the portion 14, and asilicide connection 136 is furthermore established between the two uppersilicon portions 13 a and 13 b.

[0092] No silicide formation reaction takes place on the other partscovered with metal 6, such as the upper surface and the portions of thewall of the cavity that are adjacent to the silicon volume 12, togetherwith the bottom of the cavity C formed by the insulation layer 101. Theprocess therefore allows silicide portions to be formed selectively inregions characterized by the presence of silicon. Outside these regions,the presence of silica SiO₂ inhibits silicide formation. Silicon nitrideSi₃N₄ or any other material different from pure silicon, or siliconincorporating a small proportion of foreign atoms, also preventssilicide formation.

[0093] The excess metal 6 is finally removed by chemically dissolving itusing a suitable etching solution, in the manner described above. Theconfiguration in FIG. 13 is then obtained, which has two contact regions146 and 156 and two connections 106 and 136. Thanks to the process ofthe invention, these contact regions and these connections have beenproduced simultaneously in parts of the circuit that are separate anddistributed in any fashion, according to the design of the circuit.

[0094] Although preferred embodiments of the method and apparatus of thepresent invention have been illustrated in the accompanying Drawings anddescribed in the foregoing Detailed Description, it will be understoodthat the invention is not limited to the embodiments disclosed, but iscapable of numerous rearrangements, modifications and substitutionswithout departing from the spirit of the invention as set forth anddefined by the following claims.

What is claimed is:
 1. A process for forming at least one portion of acompound material formed from elements of an initial material and of ametal within an electronic circuit, comprising the following steps: (a)formation of a cavity that includes at least one opening onto an accesssurface and has an internal wall having at least one region of initialmaterial; (b) deposition of the metal close to said region of initialmaterial; (c) heating of the circuit so as to form a portion of compoundmaterial in said region of initial material; and (d) removal of at leastone portion of the metal that has not formed some of the compoundmaterial from the cavity via said opening.
 2. The process according toclaim 1, wherein step (a) comprises the removal of at least one materialfrom the circuit.
 3. The process according to claim 1, wherein step (a)comprises the transfer of at least one material from a temporarysubstrate to a final substrate carrying the electronic circuit.
 4. Theprocess according to claim 1, wherein the initial material comprisessilicon, germanium, arsenic, selenium, or a mixed compound comprising atleast one of the above elements.
 5. The process according to claim 1,wherein step (b) comprises introducing the metal into the cavity via theopening so as to form a deposition of the metal on at least said regionof initial material.
 6. The process according to claim 1, wherein step(b) comprises depositing the metal outside the cavity close to saidopening and wherein, during step (c), the metal diffuses into thecavity, via said opening of the cavity, as far as said region of initialmaterial, so as to form a portion of the compound material in saidregion of initial material.
 7. The process according to claim 1, whereinstep (b) comprises a chemical deposition of the metal from gaseousprecursor compounds incorporating atoms of the metal, or a depositionusing a liquid solution introduced into the cavity and incorporatingdissolved chemical compounds based on the metal in an oxidized form. 8.The process according to claim 1, wherein the metal comprises cobalt,tantalum, tungsten, titanium, aluminium, copper, silver, platinum,nickel or an alloy comprising at least one of the above metals.
 9. Theprocess according to claim 1, wherein the compound material formed iselectrically conducting.
 10. The process according to claim 1, whereinstep (d) comprises an etching by means of a solution including chemicalreactants.
 11. The process according to claim 1, wherein, during step(c), substantially all the initial material present in said region ofinitial material is converted into compound material.
 12. The processaccording to claim 1, wherein the internal wall of the cavity has atleast two regions of initial material separated by an intermediateregion of a material other than the initial material and wherein, duringstep (c), the initial material of at least one of said regions ofinitial material is made to diffuse into the metal so as to form aportion of compound material connecting said regions of initialmaterial.
 13. The process according to claim 1, wherein the internalwall of the cavity has a region of silica or of silicon nitride.
 14. Theprocess according to claim 1, wherein the cavity comprises a cylindricalor parallelepipedal first volume open to the access surface.
 15. Theprocess according to claim 14, wherein the cavity furthermore comprisesa second volume into which the first volume runs on the opposite sidefrom the access surface, the second volume extending further than thefirst volume parallel to the access surface.
 16. An electronic circuitincluding a portion of compound material manufactured by the process ofclaim
 1. 17. The electronic circuit according to claim 16, wherein theportion of compound material comprises at least one electricalconnection.
 18. An MOS transistor including a gate having a portion ofcompound material manufactured by the process of claim
 1. 19. The MOStransistor according to claim 18, wherein the compound material has awork function within a range of ±25% around a mean value of two workfunctions of a p-type semiconductor material and an n-type semiconductormaterial, respectively.
 20. An electronic circuit including an MOStransistor having a gate with a portion of compound materialmanufactured by the processing of claim
 18. 21. A process for MOStransistor gate formation, comprising the steps of: depositing atemporary material; forming a transverse structure including a siliconbar doped to define source, drain and channel regions; removing thetemporary material from under the transverse structure to define acavity; depositing a metal on exposed surfaces of the transversestructure and in the cavity; and heating to convert the portions of thesilicon bar adjacent to deposited metal into silicide.
 22. The method ofclaim 21 further including removing the deposited metal which is notconverted to silicide by heating.
 23. The method of claim 21 whereinheating converts certain portions of the silicon bar to define sourceand drain electrical contacts of the transistor.
 24. The method of claim21 wherein heating converts certain portions of the silicon bar todefine a gate surrounding the channel region.
 25. The MOS transistorformed by using the method of claim
 21. 26. A process for producingelectrical connections between separate circuit portions, comprising:defining first and second separate silicon portions; depositing a metaloverlying the first and second separate silicon portions and a structuretherebetween; and heating to convert portions of the first and secondsilicon portions adjacent to deposited metal into silicide, wherein thesilicide from the first and second silicon portions connects.
 27. Theprocess of claim 26 wherein the first and second separate siliconportions may be vertically separated.
 28. The process of claim 26wherein the first and second separate silicon portions may behorizontally separated.
 29. The process of claim 26 further including:forming a temporary material adjacent the first and second separatesilicon portions; burying the temporary material and first and secondseparate silicon portions with a covering material; forming a chimneythrough the covering material to reach the temporary material; andremoving the temporary material through the chimney to form a cavity.30. The process of claim 29 wherein depositing comprises depositing themetal through the chimney to at least partially fill the cavity.
 31. Themethod of claim 26 further including removing the deposited metal whichis not converted to silicide by heating.
 32. The electrical connectionformed by using the method of claim 26.